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1. general description the nvt2008/10 are bidirectional voltage level translators operational from 1.0 v to 3.6 v (v ref(a) ) and 1.8 v to 5.5 v (v ref(b) ), which allow bidirectional voltage translations between 1.0 v and 5 v without the need for a directio n pin in open-drain or push-pull applications. bit widths of 8-bit to 10-bit are offered for level translation application with transmission speeds < 33 mhz for an open-drain system with a 50 pf capacitance and a pull-up of 197 . when the an or bn port is low, the clamp is in the on-state and a low resistance connection exists between the an and bn ports. the low on-state resistance (r on ) of the switch allows connections to be made with minimal propagation delay. assuming the higher voltage is on the bn port when the bn po rt is high, the voltage on the an port is limited to the voltage set by vrefa. when the an port is high, the bn port is pulled to the drain pull-up supply voltage (v pu(d) ) by the pull-up resistors. this functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. when en is high, the translator switch is on , and the an i/o are connected to the bn i/o, respectively, allowing bidirectional data flow between ports. when en is low, the translator switch is off, and a high-impedance state exists between ports. the en input circuit is designed to be supplied by v ref(b) . to ensure the high-impedance state during power-up or power-down, en must be low. all channels have the same electrical characte ristics and there is minimal deviation from one output to another in voltage or propagat ion delay. this is a benefit over discrete transistor voltage translation solutions, since the fabrication of the s witch is symmetrical. the translator provides excellent esd prot ection to lower voltage devices, and at the same time protects less esd-resistant devices. 2. features and benefits ? provides bidirectional voltage translation with no direction pin ? less than 1.5 ns maximum propagation delay ? allows voltage level translation between: ? 1.0 v v ref(a) and 1.8 v, 2.5 v, 3.3 v or 5 v v ref(b) ? 1.2 v v ref(a) and 1.8 v, 2.5 v, 3.3 v or 5 v v ref(b) ? 1.8 v v ref(a) and 3.3 v or 5 v v ref(b) ? 2.5 v v ref(a) and 5 v v ref(b) ? 3.3 v v ref(a) and 5 v v ref(b) nvt2008; nvt2010 bidirectional voltage-level tr anslator for open-drain and push-pull applications rev. 1 ? 8 september 2010 product data sheet
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 2 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator ? low 3.5 on-state connection between input and output ports provides less signal distortion ? 5 v tolerant i/o ports to support mixed-mode signal operation ? high-impedance an and bn pins for en = low ? lock-up free operation ? flow through pinout for ease of printed-circuit board trace routing ? esd protection exceeds 4 kv hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? packages offered: tsso p20, dhvqfn20, tssop 24, dhvqfn24, hvqfn24 3. ordering information [1] gtl2003 = nvt2008. [2] gtl2010 = nvt2010. table 1. ordering information t amb = ? 40 c to +85 c. type number topside mark number of bits package name description version NVT2008BQ [1] nvt2008 8 dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm sot764-1 nvt2008pw [1] nvt2008 8 tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 nvt2010bq [2] nvt2010 10 dhvqfn24 plastic dual in-lin e compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm sot815-1 nvt2010bs [2] n010 10 hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm sot616-1 nvt2010pw [2] nvt2010 10 tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 3 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 4. functional diagram 5. pinning information 5.1 pinning 5.1.1 8-bit in tssop20 and dhvqfn20 packages fig 1. logic diagram of nv t2008/10 (positive logic) 002aae13 2 a1 an vrefa gnd vrefb b1 bn en sw sw nvt20xx fig 2. pin configuration for tssop20 fig 3. pin configuration for dhvqfn20 nvt2008pw gnd en vrefa vrefb a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 002aae225 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 002aae22 6 NVT2008BQ transparent top view b7 a6 a7 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 vrefa vrefb a8 b8 gnd en 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 4 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 5.1.2 10-bit in tssop24, dhvqfn24 and hvqfn24 packages fig 4. pin configuration for tssop24 fig 5. pin configuration for dhvqfn24 fig 6. pin configuration for hvqfn24 nvt2010pw gnd en vrefa vrefb a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 002aae227 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aae22 8 nvt2010bq transparent top view b9 a8 a9 b8 a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 vrefa vrefb a10 b10 gnd en 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 12 13 1 24 terminal 1 index area 002aae22 9 nvt2010bs transparent top view b10 a3 a4 b9 a2 b8 a1 b7 vrefa b6 gnd b5 a5 a6 a7 a8 a9 a10 en vrefb b1 b2 b3 b4 terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 5 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 5.2 pin description [1] 8-bit nvt2008 available in tssop20, dhvqfn20 packages. [2] 10-bit nvt2010 available in tsso p24, dhvqfn24, hvqfn24 packages. table 2. pin description symbol pin description nvt2008 [1] nvt2010 [2] gnd 1 1 ground (0 v) vrefa 2 2 low-voltage side reference supply voltage for an a1 - - low-voltage side; connect to vrefa through a pull-up resistor a1 to an 3, 4, 5, 6, 7, 8, 9, 10 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 b1 - - high-voltage side; connect to vrefb through a pull-up resistor b1 to bn 18, 17, 16, 15, 14, 13, 12, 11 22, 21, 20, 19, 18, 17, 16, 15, 14, 13 vrefb 19 23 high-voltage side reference supply voltage for bn en 20 24 switch enable input; connect to vrefb and pull-up through a high resistor
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 6 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 6. functional description refer to figure 1 ? logic diagram of nvt2008/10 (positive logic) ? . 6.1 function table [1] en is controlled by the v ref(b) logic levels and should be at least 1 v higher than v ref(a) for best translator operation. 7. application design-in information the nvt2008/10 can be used in level translat ion applications for interfacing devices or systems operating at different interface vo ltages with one another. the nvt2008/10 is ideal for use in applications where an open-drain driver is connected to the data i/os. the nvt2008/10 can also be used in applications where a push-pull driver is connected to the data i/os. 7.1 enable and disable the nvt20xx has an en input that is used to disable the device by setting en low, which places all i/os in the high-impedance state. table 3. function selection (example) h = high level; l = low level. input en [1] function han=bn l disconnect (1) the applied voltages at v ref(a) and v pu(d) should be such that v ref(b) is at least 1 v higher than v ref(a) for best translator operation. fig 7. typical application ci rcuit (switch always enabled) 002aae13 4 a1 a2 vrefa gnd 3 4 vrefb 1 6 5 b1 b2 8en sw sw nvt2002 7 200 k r pu r pu v pu(d) = 3.3 v (1) i 2 c-bus device scl sda v cc gnd 2 v ref(a) = 1.8 v (1) r pu r pu i 2 c-bus master scl sda v cc gnd
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 7 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator [1] all typical values are at t amb =25 c. table 4. application operating conditions refer to figure 7 . symbol parameter conditions min typ [1] max unit v ref(b) reference voltage (b) v ref(a) +0.6 2.1 5 v v i(en) input voltage on pin en v ref(a) +0.6 2.1 5 v v ref(a) reference voltage (a) 0 1.5 4.4 v i sw(pass) pass switch current - 14 - ma i ref reference current transistor - 5 - a t amb ambient temperature operating in free-air ? 40 - +85 c (1) in the enabled mode, the applied enable voltage v i(en) and the applied voltage at v ref(a) should be such that v ref(b) is at least 1 v higher than v ref(a) for best translator operation. (2) note that the enable time and the disable time are essentially controlled by the rc time constant of the capacitor and the 200 k resistor on the en pin. fig 8. typical applic ation circuit (switch enable control) 002aae13 5 a1 a2 vrefa gnd 3 4 vrefb 1 6 5 b1 b2 8en sw sw nvt2002 7 200 k r pu r pu v pu(d) = 3.3 v i 2 c-bus device scl sda v cc gnd 2 v ref(a) = 1.8 v (1) r pu r pu i 2 c-bus master scl sda v cc gnd on off 3.3 v enable signal (1) (2)
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 8 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 7.2 bidirectional translation for the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the en input must be connected to vrefb and both pins pulled to high side v pu(d) through a pull-up resistor (typically 200 k ). this allows vrefb to regulate the en input. a filter capacitor on vrefb is recommended. the master output driver can be totem pole or open-drain (pull-up resistors may be required) and the slave device output can be totem pole or open-drain (pull-up resistors are required to pull the bn outputs to v pu(d) ). however, if either outp ut is totem-pole, data mu st be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. if both outputs are open-drain, no direction control is needed. the reference supply voltage (v ref(a) ) is connected to the processor core power supply voltage. when vrefb is connected through a 200 k resistor to a 3.3 v to 5.5 v v pu(d) power supply, and v ref(a) is set between 1.0 v and (v pu(d) ? 1 v), the output of each an has a maximum output voltage equal to vrefa, and the output of each bn has a maximum output voltage equal to v pu(d) . fig 9. bidirectional translation to multiple higher voltage levels en vrefb 002aae13 3 b1 b2 200 k chipset i/o v cc 5 v totem pole or open-drain i/o gnd vrefa a1 a2 b3 v cc bn 3.3 v a3 an cpu i/o v core 1.8 v 1.5 v 1.2 v 1.0 v sw nvt20xx sw sw chipset i/o sw b4 a4 b5 a5 sw sw b6 a6 sw
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 9 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 7.3 bidirectional level shifting be tween two different power domains nominally at the same potential the less obvious application for the nvt2008/ nvt2010 is for level shifting between two different power domains that are nominally at the same potential, such as a 3.3 v system where the line crosses power supply domains that under normal operation would be at 3.3 v, but one could be at 3.0 v and the other at 3.6 v, or one could be experiencing a power failure while the other doma in is trying to operate. one of the channel transistors is used as a second reference transistor with its b side connected to a voltage supply that is at least 1 v (and preferably 1.5 v) abov e the maximum possible for either v pu(a) or v pu(b) . then if either pull-up voltage is at 0 v, the channels are disabled, and otherwise the channels are biased such that they turn off at the lower pull-up voltage, and if the two pull-up voltages are equal, the channel is biased such that it just turns off at the common pull-up voltage. 7.4 sizing pull-up resistor the pull-up resistor value needs to limit the cu rrent through the pass transistor when it is in the on state to about 15 ma. this ensures a pass voltage of 260 mv to 350 mv. if the current through the pass transistor is higher than 15 ma, the pass voltage also is higher in the on state. to set the current through each pass transistor at 15 ma, the pull-up resistor value is calculated as: ta b l e 5 summarizes resistor reference voltages and currents at 15 ma, 10 ma, and 3 ma. the resistor values shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mv or less. the external driver the applied enable voltage v pu(h) and the applied voltage at v ref(a) and v ref(b) should be such that v ref(h) is at least 1 v higher than v ref(a) and v ref(b) for best translator operation. fig 10. bidirectional level shifting between two different power domains 002aae96 7 a1 a2 vrefa gnd 3 4 vrefb 1 8 7 b1 b2 10 en sw sw nvt2003 9 200 k r pu r pu v pu(b) = 3.3 v i 2 c-bus device scl sda v cc gnd 2 v pu(a) = 3.3 v r pu r pu i 2 c-bus master scl sda v cc gnd v pu(h) a3 5 6 sw b3 v pu(b) r pu v pu d () 0.35 v ? 0.015 a ------------------------------------- - =
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 10 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator must be able to sink the total current from the resistors on both sides of the nvt20xx device at 0.175 v, although the 15 ma only applies to current flowing through the nvt20xx device. [1] +10 % to compensate for v cc range and resistor tolerance. 7.4.1 maximum frequency calculation the maximum frequency is totally dependent u pon the specifics of th e application and the device can operate > 33 mhz. basically, the nvt20xx behaves like a wire with the additional characteristics of tr ansistor device physics and should be capable of performing at higher frequencies if used correctly. here are some guidelines to follow that will help maximize th e performance of the device: ? keep trace length to a minimum by plac ing the nvt20xx close to the processor. ? the trace length should have a time of flight less than half of the transition time to reduce ringing and reflections. ? the faster the edge of the signal, the higher the chance for ringing. ? the higher the drive strength (up to 15 ma), the higher the frequency the device can use. in a 3.3 v to 1.8 v direction level shift, if the 3.3 v side is being driven by a totem pole type driver no pull-up resistor is needed on the 3.3 v side. the capacitance and line length of concern is on the 1.8 v side since it is driv en through the on resistance of the nvt20xx. if the line length on the 1.8 v side is long enough there can be a reflection at the chip/terminating end of the wire when the transition time is shorter than the time of flight of the wire because the nvt20xx looks like a hi gh-impedance compared to the wire. if the wire is not too long and the lum ped capacitance is not excess ive the signal will only be slightly degraded by the series resistance added by passing through the nvt20xx. if the lumped capacitance is large the rise time will deteriorate, the fall time is much less affected and if the rise time is slowed down too much the duty cycle of the clock will be degraded and at some point the clock will no longer be useful. so the principle design consideration is to minimize the wire length and the capacitance on the 1.8 v side for the clock path. a pull-up resistor on the 1.8 v side can also be used to trade a slower fall time for a faster rise time and can also reduce the overshoot in some cases. table 5. pull-up resistor values calculated for v ol = 0.35 v; assumes output driver v ol = 0.175 v at stated current. v pu(d) pull-up resistor value ( ) 64 ma 32 ma 15 ma 10 ma 3ma nominal +10 % [1] nominal +10 % [1] nominal +10 % [1] nominal +10 % [1] nominal +10 % [1] 5 v 310 341 465 512 1550 1705 3.3 v 197 217 295 325 983 1082 2.5 v 143 158 215 237 717 788 1.8 v 97 106 145 160 483 532 1.5 v 77 85 115 127 383 422 1.2 v 57 63 85 94 283 312
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 11 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 7.4.1.1 example maximum frequency question ? we need to make the pll area of a new line card backwards compatible and need to need to convert one gtl signal to lvttl, invert it, and convert it back to gtl. the signal we want to conver t is random in nature but will mostly be around 19 mhz with very long periods of inactivity where either a high or low state will be maintained. the traces are 1 or 2 inches long with trace capacitance of about 2 pf per inch. answer ? the frequency of the nvt20xx is limited by the capacitance of the part, the capacitance of the traces and the pull-up resistors used. the limiting case is probably the low-to-high transition in the gtl to lvttl direction, and there the use of the lowest acceptable resistor values will minimize the ri se time delay. assuming 50 pf capacitance and 220 resistance, the rc time constant is 11 ns (50 pf 220 ). with 19 mhz corresponding to 50 ns period the nvt20xx will support this application. 8. limiting values [1] the input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed. [2] low duty cycle pulses, not dc because of heating. 9. recommended operating conditions [1] v ref(a) v ref(b) ? 1 v for best results in level shifting applications. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). over operating free-air temperature range. symbol parameter conditions min max unit v ref(a) reference voltage (a) ? 0.5 +6 v v ref(b) reference voltage (b) ? 0.5 +6 v v i input voltage ? 0.5 [1] +6 v v i/o voltage on an input/output pin ? 0.5 [1] +6 v i ch channel current (dc) - 128 ma i ik input clamping current v i <0v ? 50 - ma i ok output clamping current [2] ? 50 +50 ma t stg storage temperature ? 65 +150 c table 7. operating conditions symbol parameter conditions min max unit v i/o voltage on an input/output pin an, bn 0 5.5 v v ref(a) [1] reference voltage (a) vrefa 0 5.4 v v ref(b) [1] reference voltage (b) vrefb 0 5.5 v v i(en) input voltage on pin en 0 5.5 v i sw(pass) pass switch current - 64 ma t amb ambient temperature operating in free-air ? 40 +85 c
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 12 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 10. static characteristics [1] all typical values are at t amb =25 c. [2] not production tested, maximum value based on characterization data of typical parts. [3] measured by the voltage drop between the an and bn terminals at the indicated current through the switch. on-state resistanc e is determined by the lowest voltage of the two terminals. [4] see curves in figure 11 for typical temperature and v i(en) behavior. [5] guaranteed by design. table 8. static characteristics t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v ik input clamping voltage i i = ? 18 ma; v i(en) =0v - - ? 1.2 v i ih high-level input current v i =5v; v i(en) =0v --5 a c i(en) input capacitance on pin en v i = 3 v or 0 v - 17 - pf c io(off) off-state input/output capacitance an, bn; v o =3vor0v; v i(en) =0v - 56pf c io(on) on-state input/output capacitance an, bn; v o =3vor0v; v i(en) =3v -11.513 [2] pf r on on-state resistance [3] [4] an, bn; v i =0v;i o =64ma; v i(en) =4.5v [5] 12.75.0 v i =2.4v; i o =15ma; v i(en) =4.5v -4.87.5
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 13 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator a. i o =64ma; v i =0v b. i o =15ma; v i =2.4v; v i(en) =4.5v c. i o =15ma; v i = 2.4 v; v i(en) =3.0v d. i o =15ma; v i =1.7v; v i(en) =2.3v fig 11. typical on-state resistance versus ambient temperature t amb ( c) ? 40 100 ? 20 002aaf697 0 20 40 60 80 4 6 2 8 10 r on(typ) ( ) 0 v i(en) = 1.5 v 2.3 v 3.0 v 4.5 v t amb ( c) ? 40 100 ? 20 002aaf698 0 20 40 60 80 2 8 r on(typ) ( ) 0 6 4 t amb ( c) ? 40 100 ? 20 002aaf699 0 20 40 60 80 20 80 r on(typ) ( ) 0 60 40 t amb ( c) ? 40 100 ? 20 002aaf700 0 20 40 60 80 20 80 r on(typ) ( ) 0 60 40
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 14 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 11. dynamic characteristics 11.1 open-drain drivers [1] see graphs based on r on typical and c io(on) +c l =50pf. table 9. dynamic characteristics for open-drain drivers t amb = ? 40 cto+85 c; v i(en) =v ref(b) ; r bias(ext) = 200 k ; c vrefb =0.1 f; unless otherwise specified. symbol parameter conditions min typ max unit refer to figure 14 t plh low to high propagation delay from (input) bn to (output) an [1] r on (c l + c io(on) )ns t phl high to low propagation delay from (input) bn to (output) an r on (c l + c io(on) )ns fig 12. ac test setup fig 13. example of typical ac waveform 002aaf34 7 dut en vrefb vrefa 1.5 v 200 k signal generator 5.5 v 0.1 f 1.5 v swing 50 pf 450 500 6.6 v 1 v/div 40 ns/div 002aaf348 bn an gnd gnd a. load circuit b. timing diagram; high-impedance scope probe used s2 = translating down, and same voltage. c l includes probe and jig capacitance. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 ; t r 2ns; t f 2ns. the outputs are measured one at a time, with one transition per measurement. fig 14. load circuit for outputs 002aab84 5 v tt r l s1 s2 (open) c l from output under test 002aab846 v ih v il v m v m input output v oh v ol v m v m
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 15 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 12. performance curves t plh up-translation is typically dominate d by the rc time constant, i.e., c l(tot) r pu =50pf 197 = 9.85 ns, but the r on c l(tot) =50pf 5 =0.250ns. t phl is typically dominated by the external pull-down driver + r on , which is typically small compared to the t plh in an up-translation case. enable/disable times are dominated by the rc time constant on the en pin since the transistor turn off is on the order of ns , but the enable rc is on the order of ms. fall time is dominated by the external pull-down driver with only a slight r on addition. rise time is dominated by the r pu c l . skew time within the part is virtually non- existent, dominated by the difference in bond wire lengths, which is typically small compar ed to the board-level routing differences. maximum data rate is dominated by the system capacitance and pull-up resistors. (1) v i(en) = 1.5 v; i o =64ma; v i =0v. (2) v i(en) = 4.5 v; i o =15ma; v i =2.4v. (3) v i(en) = 2.3 v; i o =64ma; v i =0v. (4) v i(en) = 3.0 v; i o =64ma; v i =0v. (5) v i(en) = 4.5 v; i o =64ma; v i =0v. (1) v i(en) = 3.0 v; i o =15ma; v i =2.4v. (2) v i(en) = 2.3 v; i o =15ma; v i =1.7v. fig 15. typical capacitance versus propagation delay 0.2 0.4 0.6 t pd (ns) 0 c (pf) 0 100 80 40 60 20 002aaf701 (1) (2) (3) (4) (5) 1 2 3 t pd (ns) 0 c (pf) 0 100 80 40 60 20 002aaf702 (1) (2)
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 16 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 13. package outline fig 16. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764- 1 d hvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 2 0 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 17 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator fig 17. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360 -1 a max. 1.1
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 18 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator fig 18. package outline sot815-1 (dhvqfn24) references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. sot815-1 - - - - - - - - - 03-04-29 sot815 -1 0 2.5 5 mm scale b y y 1 c c a c c b v m w m e 1 e 2 terminal 1 index area terminal 1 index area x unit a (1) max. a 1 bc e e h l e 1 y w v mm 1 0.05 0.00 0.30 0.18 0.5 4.5 e 2 1.5 0.2 2.25 1.95 d h 4.25 3.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 d (1) 5.6 5.4 e (1) 3.6 3.4 d e b a e d hvqfn24: plastic dual in-line compatible thermal enhanced very thin quad flat package; n o leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm a a 1 c detail x e h l d h 2 23 11 14 13 12 1 24
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 19 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator fig 19. package outline sot616-1 (hvqfn24) 0.5 1 0.2 a 1 e h b unit y e references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.25 1.95 y 1 4.1 3.9 2.25 1.95 e 1 2.5 e 2 2.5 0.30 0.18 c 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot616-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot616 -1 h vqfn24: plastic thermal enhanced very thin quad flat package; no leads; 2 4 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 712 24 19 18 13 6 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area a c c b v m w m 1/2 e 1/2 e e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 20 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator fig 20. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355 -1 a max. 1.1
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 21 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 22 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 0 and 11 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 21 . table 10. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 11. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 23 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations 16. revision history msl: moisture sensitivity level fig 21. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 12. abbreviations acronym description cdm charged device model esd electrostatic discharge gtl gunning transceiver logic hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output lvttl low voltage transistor-transistor logic mm machine model prr pulse repetition rate rc resistor-capacitor network table 13. revision history document id release date data sheet status change notice supersedes nvt2008_nvt2010 v.1 20100908 product data sheet - -
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 24 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator 17. legal information 18. data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
nvt2008_nvt2010 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 1 ? 8 september 2010 25 of 26 nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors nvt2008; nvt2010 bidirectional voltage-level translator ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 september 2010 document identifier: nvt2008_nvt2010 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.1.1 8-bit in tssop20 and dhvqfn20 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.1.2 10-bit in tssop24, dhvqfn24 and hvqfn24 packages . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 application design-in information . . . . . . . . . . 6 7.1 enable and disable . . . . . . . . . . . . . . . . . . . . . . 6 7.2 bidirectional translation . . . . . . . . . . . . . . . . . . 8 7.3 bidirectional level shifting between two different power domains nominally at the same potential . . . . . . . . . . . . . . . . . . . . 9 7.4 sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 9 7.4.1 maximum frequency calculation . . . . . . . . . . . 10 7.4.1.1 example maximum frequency . . . . . . . . . . . . 11 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 9 recommended operating conditions. . . . . . . 11 10 static characteristics. . . . . . . . . . . . . . . . . . . . 12 11 dynamic characteristics . . . . . . . . . . . . . . . . . 14 11.1 open-drain drivers . . . . . . . . . . . . . . . . . . . . . 14 12 performance curves . . . . . . . . . . . . . . . . . . . . 15 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 soldering of smd packages . . . . . . . . . . . . . . 21 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 21 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 21 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 24 18 data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 18.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 18.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 18.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 19 contact information. . . . . . . . . . . . . . . . . . . . . 25 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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